Integrated circuit with pads connected by an under-bump metallization and method for production thereof

ABSTRACT

A semiconductor device includes a semiconductor chip. External connection pads and further pads are disposed over a surface of the semiconductor chip. Selected ones of the further pads are electrically connected to one another so as to activate selected functions within the semiconductor chip.

This is a divisional application of U.S. application Ser. No.11/409,255, which was filed on Apr. 21, 2006 now U.S. Pat. No.7,919,363, which is a continuation of International Application No.PCT/DE2004/002284, filed Oct. 14, 2004, which designated the UnitedStates and was not published in English, and which is based on GermanApplication No. 103 49 749.8 filed Oct. 23, 2003, all of whichapplications are incorporated herein by reference.

TECHNICAL FIELD

The invention relates to an antifuse connection for integrated circuitsfor the activation of redundant circuits or chip functions of flip-chiparrangements with an under-bump metallization on standard pads on thesurface of a chip for the incorporation of bumps, and to a method forproduction of such antifuse connections.

BACKGROUND

Redundant circuits are usually concomitantly integrated in integratedcircuits in order to be able to activate these as required. Suchredundant circuits are activated if individual circuit parts are notfunctional on account of a defective processing (e.g., defects,particles). The redundant circuits then undertake the task of thedefective circuits and the overall chip is fully functional.

In order to activate the redundant circuit, the integrated circuit hasto be electrically isolated from the defective region and be connectedto a redundant circuit (replacement circuit). This is done by means offuses for isolating current paths and antifuses for connecting currentpaths.

An example of a fuse and an antifuse and also a method for productionand activation of a fuse and an antifuse emerge from German patentapplication 196 04 776 A1 and corresponding PCT application WO 97/29515.

These fuses have hitherto been integrated in the metallization layers ofthe integrated circuit. In order to isolate a fuse, then, a laser beamis directed onto it and the fuse is blown. What is problematic in thiscase is that the fuse is encapsulated in a dielectric, so that theencapsulating dielectric layer often bursts open during the fuse blowingoperation. This then results in reliability problems such as leakagecurrents, corrosion, etc.

After the processing of the chips has finished, the chips areelectrically checked for functionality prior to mounting into a housing.Non-functioning chips are repaired with the fuses as above before theyare mounted into housings.

SUMMARY OF THE INVENTION

The invention is based on the object, then, of providing an antifuseconnection for integrated circuits for the activation of redundantcircuits, which can be provided with little outlay and in the case ofwhich the problems that can be noted in the prior art do not occur.Furthermore, the intention is to demonstrate a method by which suchantifuse connections can be produced.

The object on which the invention is based is achieved by virtue of thefact that further mini-pads are arranged on the surface of the chipalongside the standard pads. The further mini-pads are electricallyconnected to functional units in the chip. Selected mini-pads areconnected to one another by antifuse connections patterned from theunder-bump metallization.

Reliability problems are thus avoided because the antifuses are producedby normal patterning of the UBM metallization and a high-energy laserprocessing is unnecessary.

The object on which the invention is based is furthermore achieved bymeans of a method for production of antifuse connections, that ischaracterized in that firstly the UBM metallization is deposited on thechip and a photoresist layer is deposited on the metallization and theregions of the standard pads are exposed. Subsequently, the areasrequired for the antifuse connections are additionally exposed by meansof a laser or an electron beam. Afterward, the photoresist is developedand the UBM metallization including the antifuse connections ispatterned.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be explained in more detail below using an exemplaryembodiment. In the associated figures of the drawing:

FIG. 1 shows a finished processed chip with standard pads and additionalmini-pads for UBM (anti) fuses;

FIG. 2 shows the finished processed chip according to FIG. 1, after theapplication and patterning of the UBM metallization and with additionalUBM antifuse connections;

FIG. 3 shows a finished processed chip with a patterned UBMmetallization, solder bumps and a printed circuit board; and

FIG. 4 shows a finished process chip with a patterned UBM metallization,solder bumps and a lead frame.

THE FOLLOWING LIST OF REFERENCE SYMBOLS CAN BE USED IN CONJUNCTION WITHTHE FIGURES

-   -   1 Standard pad    -   2 Chip    -   3 UBM metallization    -   4 Mini-pad    -   5 Antifuse connection

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

In the case of the invention described below, a metallization plane,which is used for the application of so-called bumps onto the standardpads 1 on a chip 2 of a flip-chip metallization (UBM: under-bumpmetallization), is utilized for the formation of fuses or antifuses.After the processing of the wafer has finished, this UBM metallization 3is deposited in planar fashion on the wafer and, as a result of asubsequent patterning, is left only above the standard pads 1. In afurther step, bumps (not illustrated) are then applied to the standardpads 1, by means of which bumps the chip 2 can then be electricallycontact-connected to a leadframe or a printed circuit board.

According to FIG. 1, additional mini-pads 4 are provided, which havebeen led over the product to the top side of the chip 2. The UBMmetallization layer can thus be utilized for producing electricallyconductive antifuse connections 5 between the mini-pads 4. In this case,selected mini-pads 4 are short-circuited by the antifuse connections 5(FIG. 2).

The particular advantage of this “antifusing” can be seen in the factthat it is possible to correct the circuit up to directly prior to thepackaging of the circuit, that is to say the mounting of the chip 2 on aleadframe and subsequent molding (encapsulation), that is to say up tothe concluding UBM deposition and patterning.

A further advantage lies in the fact that the “antifusing” according tothe invention cannot lead to any reliability problems whatsoever in thechip 2 since the antifuse connections 5 are situated on the surface ofthe chip 2 and are only deposited at the required locations.

Furthermore, in contrast to the laser fuses used hitherto, active orpassive components can also be arranged under the antifuse connections5.

The UBM metallization can be used according to the invention for theantifuse connections 5 described and also for programming the circuit.That is to say, the function of the chip can be defined in terms ofhardware here in the case of chips with a plurality of functions outsidethe production line. Furthermore, the UBM metallization can be used as achip wiring plane, as a result of which a metallization plane can beobviated, which leads to a significant saving of costs.

Before the patterning of the UBM metallization is performed, all thechips 2 on a wafer are tested with regard to their functionality.Afterward, the UBM metallization is deposited and a photoresist layer isdeposited thereon and the regions of the standard pads 1 are exposed,but are not yet developed. Afterward, the areas required for theantifuse connections 5 are then additionally exposed for example bymeans of a laser or an electron beam. Afterward, the photoresist is thendeveloped and the UBM metallization is patterned. This is then followedby the further processes required for flip-chip mounting.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor chip; first connection pads disposed on a surface of thesemiconductor chip; second connection pads disposed on the surface ofthe semiconductor chip; functional units connected to the secondconnection pads, wherein selected function units of the functional unitscomprise redundant circuitry; and an under-bump metallization layerdisposed on the semiconductor chip such that selected ones of the secondconnection pads are electrically connected to one another.
 2. The deviceof claim 1, wherein the selected ones of the second connection pads areelectrically connected to one another so as to program the semiconductorchip.
 3. The device of claim 1, further comprising solder bumps disposedover the first connection pads.
 4. The device of claim 3, furthercomprising a printed circuit board connected to the solder bumps.
 5. Thedevice of claim 1, wherein the first connection pads are arrangedalongside opposite edges of the semiconductor chip and wherein thesecond connection pads are arranged in a central region of thesemiconductor chip between the first connection pads.
 6. The device ofclaim 1, wherein the seconds connection pads are smaller than the firstconnection pads.
 7. An integrated circuit comprising: a semiconductorchip; first under-bump metallization pads formed over first pads on asurface of the semiconductor chip, the first under-bump metallizationpads configured to receive solder bumps; and at least one under-bumpmetallization antifuse connection connecting selected ones of secondpads on the surface of the semiconductor chip.
 8. The integrated circuitof claim 7, wherein the first pads are larger than the second pads. 9.The integrated circuit of claim 7, wherein the at least one under-bumpmetallization antifuse connection connects the selected ones of thesecond pads based on test results derived from testing the semiconductorchip.
 10. The integrated circuit of claim 7, wherein the at least oneunder-bump metallization antifuse connection connects the selected onesof the second pads to enable redundant circuitry within thesemiconductor chip.
 11. The integrated circuit of claim 7, wherein thefirst pads are located along a periphery of the semiconductor chip. 12.A packaged device comprising: a semiconductor chip; under-bumpmetallization connection pads disposed on the semiconductor chip; and atleast one under-bump metallization antifuse connection, the under-bumpmetallization antifuse connection connecting selected functional unitsin the semiconductor chip.
 13. The device of claim 12, wherein theunder-bump metallization connection pads are located along an edge ofthe semiconductor chip.
 14. The device of claim 12, further comprisingstandard pads underlying the under-bump metallization connection pads,wherein the at least one under-bump metallization antifuse connectionconnects selected ones of further pads disposed on the semiconductorchip.
 15. The device of claim 14, wherein the further pads are locatedin a center region of the semiconductor chip.
 16. The device of claim15, wherein the further pads are smaller than the standard pads.
 17. Thedevice of claim 12, further comprising a printed circuit board connectedto the semiconductor chip via the under-bump metallization connectionpads.
 18. The device of claim 17, wherein the printed circuit board issoldered to the semiconductor chip at the under-bump metallizationconnection pads.
 19. A semiconductor device comprising: a semiconductorchip; first connection pads disposed on a surface of the semiconductorchip; second connection pads disposed on the surface of thesemiconductor chip; and an under-bump metallization layer disposed onthe semiconductor chip such that selected ones of the second connectionpads are electrically connected to one another so as to program thesemiconductor chip.